1. Field of the Invention
The invention relates to a clock control circuit for a digital system, and particularly to a circuit for turning on and off a clock without a glitch.
2. Discussion of the Related Art
Integrated circuits (ICs) typically comprise multiple combinatorial and sequential logic circuits. Combinatorial logic circuits contain logic gates, but not storage elements, and their outputs depend only on present inputs to the circuit. Sequential logic circuits contain memory storage elements in addition to gates, and their outputs depend on prior inputs as well as current inputs. The order in which data is latched among the elements of a sequential logic circuit will thus affect the output of the circuit.
Asynchronous latches respond whenever an input signal is applied and are referred to as having "direct" inputs. A system using several such latches will have inputs arriving at various times. It is often desired, however, to use synchronous latches to ensure simultaneity and certainty in the temporal ordering of latch responses, such as with ICs containing sequential logic circuits. In these circuits, a common synchronizing clock signal is used which triggers the synchronous latches at rising (positive) and/or falling (negative) edges of its periodic waveform. Synchronized latches are thus referred to as having "clock-triggered" inputs.
Clock signals are typically generated by one or more crystals which undergo atomic oscillations at known frequencies. It is typically desired to have multiple clock frequencies for use with various sub-circuits within a single digital system. For simple circuits, it may be sufficient to use a number of different crystals each having a different frequency of oscillation. However, for complex ICs, a clocking schedule is typically employed wherein sophisticated clock signal delay and clock and input signal skewing techniques are used to stretch clock and/or input signal periods to meet the needs of each particular sub-circuit of the IC.
Delays may be produced at junctions and by varying inductances, resistances, and current densities. Delays may be incurred during transmission, propagation or queuing of signals. Josephson transmission lines have been used as well with superconducting circuitries to promote delay. Clock and input signal skewing involves a stretching of the signal period to reduce the frequency of a clock signal.
One of the goals of synthesizing a clocking schedule is to minimize the probability of "glitches" occurring during the operation of an IC. A glitch can occur when the outputs of a circuit have random values for a brief time before they settle down to correct values. If another circuit inspects the output at just the wrong time and reads the random value, the results can be very wrong and difficult to debug. For example, a glitch was cited as the cause of a systems communication problem which halted trading on the NYSE for an hour in 1998. Glitches are also known to cause unpleasant "snapping" sounds when a process of "CD grabbing" occurs during a song. Glitches have caused momentary zero voltages across electrical mains and sudden voltage increases across capacitors causing steps in affected ramps, sometimes having lasting effects including extended tails.
A first specific type of digital glitch happens when a logic threshold transition occurs more than once between fixed or specified clock periods. That is, an input signal both rises and falls, or vice-versa, between triggering clock edges and is thus not captured by the clock trigger.
A second type of digital glitch arises when a clocking edge appears between two asynchronous inputs. For example, one of the two inputs may be read as a "1" instead of a "0", as desired or expected, or vice-versa, as the logic of the circuit would dictate, yielding erroneous results. In this second case, the first latch is clock-triggered before it has had time to successfully register its input. A logical error can result when the second sequential input in a logical sequence of two asynchronous inputs is triggered before the first input has successfully registered.
A third type of glitch affecting digital circuits occurs when an external signal effects the polarity of an input for an arbitrary duration. Such an external signal may be received from a nearby circuit or sub-component of the same IC, or from external magnetic or radiative sources such as fast moving electrons and ions within the earths magnetic field. A latch may trigger during the period of influence of a glitch of this third type, and produce an erroneous output.
On another front, many digital systems include means for monitoring a circuit to determine whether the circuit is actively receiving input data for processing. When it is determined that the circuit has been inactive for a specified period of time, the clock is turned off to save power, putting the circuit into a sleep, rest or hibernation mode. At a specified input event, the clock is turned back on and the circuit awakens to again perform processing activities. Some registers and latches require time to reset and resynchronize to predetermined logic states. If a clock trigger is received before one or more digital devices have reset and/or resynchronized, i.e., too soon after the input event triggers the system to awaken from its sleep, rest or hibernation state, a glitch may occur.
It is desired to have a circuit wherein a clock signal may be turned off, and then turned back on by a triggering input event, without incurring a glitch.